That previous paper covered an approach with 10-micron pitches, which was already a 10X improvement. QMC is a new hybrid bonding technique that features sub-3 micron pitches and results in a 10X increase in power efficiency and performance density over the research Intel submitted at last year's IEDM. As the name implies, Intel's QMC aims to offer nearly the same characteristics as the interconnects that are built right into a single die. However, these approaches still result in inevitable performance, power, and cost tradeoffs, which Intel's new 'Quasi-Monolithic Chips' (QMC) 3D packaging tech looks to solve. In conclusion, chip process advances sometimes make interesting news segments but user experiences assessed earliest in third party reviews are most essential as I am sure HEXUS readers know.The overriding goal of any chiplet-based design is to preserve the best attributes of the power consumption and performance (latency, bandwidth) of the data pathways inside of a single-die monolithic processor while tapping the economic benefits of using a chiplet-based approach, like increased yield from smaller dies fabbed on a leading-edge process and the ability to use older, cheaper nodes for some of the other functions that see lesser density improvements.Īs such, the battleground for semiconductor supremacy is shifting from the speed of the transistors to the performance of the interconnects, with new technologies like silicon interposers (EMIB) and hybrid bonding techniques coming to the forefront to improve economics. Again though, other factors make differences, like transistor type and chip architecture, that make direct comparisons difficult. Moving forward both Intel and TSMC are targeting approx 150MT/mm² for their upcoming 7nm and 5nm processes, respectively. Intel 10 nm and TSMC 7nm processes both produce dies with approx 90 million transistors per sq millimetre. The XXnm figure reflects process history more than progress, asserts the OC expert, and thus it isn't very useful as a metric to compare between chip makers.Īnother metric, probably worth closer consideration is transistor density, as revealed by the chip fabricators. Moreover, the relationship between node size, half-pitch, and gate length has significantly loosened since the early 1990s. Having looked at the above comparison, and highlighted it in his video, der8auer challenges the obvious conclusion that Intel 14nm+++ and TSMC 7nm are very similar in physical scale, reminding viewers that the above pictures don't fully represent the 3D structure that is so important to modern chip optimisation. Gate height is very similar but with the guidelines superimposed in the comparison below you can see that TSMC has indeed produced a processor with tighter spacing between the transistors In the main picture, above, you can see the first direct comparison you can see the transistor sizes of the two chips are very similar when the SEM zooms in to the same magnification. You can see much more about the background to this process, the SEM technology and der8auer's thinking in the previous two videos in this series Visiting Tescan Part 1, and Part 2. In order to get the Tescan labs SEM to make an effective comparison der8auer chose to slice into these halo consumer champs through their L1 cache sections. You probably expect the actual transistor size revealed by the SEM to be rather different… The former is an Intel 14nm+++ production chip and the latter made for AMD by TSMC on its 7nm process. This was an interesting exercise but in a recent YouTube video series der8auer has been leading up to a direct comparison between the current state-of-the-art Intel Core i9-10900K and the AMD Ryzen 9 3950X. Overclocking expert der8auer examined an Intel Core i7-8700K under a scanning electron microscope (SEM) a couple of years ago when that processor was one of Intel's best consumer offerings.
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